1. References
The following papers provide useful background information, for which they are incorporated herein by reference in their entirety, and are selectively referred to in the remainder of this disclosure by their accompanying reference codes in square brackets (i.e., [DCPR98] for the paper by V. Dhabolkar et al.):
[CD00] L. Chen and S. Dey. Defuse: A Deterministic Functional Self-Test Methodology for Processors. In VLSITS, pages 255-262, 2000.
[DCPR98] V. Dabholkar, S. Chakravarty, I. Pomeranz, and S. Reddy. Techniques for Minimizing Power Dissipation in Scan and Combinational Circuits During Test Application. IEEE Trans. on Computer-Aided Design of Integrated Circuit and System, Vol. 17(12), December 1998.
[Gro00] OCB Design Working Group. VSI Alliance Virtual Component Interface Standard. Virtual Socket Interface Alliance, November 2000.
[HIC01] J. -R. Huang, M. K. Iyer, and K. -T. Cheng. A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs. In VLSITS, pages 198-203, 2001.
[Inc00a] Sonics Inc. Open Core Protocol Specification 1.0. Sonics Inc, January 2000.
[Inc00b] Tensilica Inc. Xtensa Software Development Toolkit. Tensilica Inc., 2000.
[PH97] D. A. Patterson and J. L. Hennessy. Computer Organization & Design: The Hardware/Software Interface. Morgan Kaufmann, San Francisco, Calif., 1997.
[TCB00] H. C. Tsai, K. T. Cheng, and S. Bhawmik. On Improving Test Quality of Scan-Based BIST. IEEE Trans. on Computer-Aided Design of Integrated Circuit and System, Vol. 19(8): 928-938, August 2000.
2. Introduction
It should be noted that the disclosure discusses system-on-chips (SOC) in greater detail. However, a skilled artisan will know that the techniques are similar for a general circuit board. For example, instead of an SOC the technique are equally applicable to a circuit board with individual chips residing on it, with each chip being designated as a core.
Testing of complex system-on-a-chip (SOC) designs that contain a large number of heterogeneous embedded cores poses significant challenges. Use of external automatic test equipment (ATE ) to test these SOCs is becoming increasingly impractical. The basic capabilities of automatic test equipment are becoming increasingly inadequate for device scaling trends toward lower voltage, greater transistor and pincount, improved accuracy, and mixed analog/digital signals. External pattern volume required to adequately test the SOC far exceeds the memory available in state-of-the art ATE to store patterns. Large pattern sets result in impractical test application times. Embedded test techniques that incorporate micro-testers on-chip are emerging as a viable alternative to the conventional ATE-based test approach. These techniques are becoming necessary to augment the limited capabilities of ATE. Without such effort, it will be difficult to keep the SOC test costs in check.
Decreasing device feature sizes are enabling huge device transistor counts, and it is now practical to include embedded cores that primarily assist in facilitating on-chip testing. Large scale SOCs typically contain one or more stand alone on-chip processors that can also be harnessed to provide embedded test support. Utilizing on-chip micro-testers (processors or embedded test cores) to conduct test application is a cost effective alternative to traditional test methods that employ expensive ATE.
3. Background to the Technology and Related Work
In this section, we discuss several aspects of related work, including background and conventional technologies. A software-based test methodology to test bus-based SOC is also proposed in [HIC01]. The test protocol proposed in [HIC01] is intimately tied to a specific bus protocol (PCI bus). Test data is delivered to embedded cores using the PCI bus protocol. Therefore, if the communication fabric of the SOC is re-designed or refined to use the newer high-speed on chip-buses or bus hierarchies, then the entire embedded test support has to be re-designed. Most on-chip SOC communication architectures are custom designed. This is because the communication architecture can be tailored to meet specific, custom communication requirements of the embedded application implemented in the SOC.
A recent proposal [HIC01] uses multiplexers at all inputs of the embedded core to select between normal and test inputs. The additional multiplexers can adversely affect the timing of data paths by increasing the delay of critical paths during normal operation of the embedded core. For example, consider again a recent proposal for SOC testing [HIC01]. A test packet defined in [HIC01] consists of a 4-bit test command field, 9-bit sequence number field, 3-bit unused field and a test data field that occupies the rest of the packet. Since a 32-bit PCI bus architecture is assumed to be the communication fabric, only 16 bits of a bus word are used to carry test data to embedded cores. Ideally, we would like to use all bits in the word to carry test data. If the size of the packet is 32 bits, then only half of each packet is used to carry test data to embedded cores. In [HIC01], a packet consisting of less than 32 bits requires can be delivered to an embedded core in one bus transaction. However, to deliver packet that consists of more than 32 bits of test data, a PCI burst mode is used. During a burst, a bus master holds the bus for multiple bus cycles, and a word of data is sent to the embedded core during every cycle. Since the receiver usually requires multiple bus cycles to process one word of data, data received during burst mode has to stored in buffers. These buffers result in a significant test logic area overhead. This overhead is more for cores that require a large amount of test data.